This invention relates to integrated circuits, and more particularly to an input structure which is highly impervious to damage caused by electrostatic discharge (ESD).
Semiconductor devices and integrated circuits in particular are highly susceptible to damage from electrostatic discharge. ESD can occur from a number of sources, but a major source is static electricity generated by persons handling the integrated circuits. It is not uncommon for a person to be charged with static electricity to a potential of hundreds or even thousands of volts. When a person charged to such a potential touches an integrated circuit, the integrated circuit is often damaged. This causes serious problems in manufacturing and distribution systems, where yield is decreased. Perhaps a more serious problem is that some parts are destroyed after testing, thereby allowing faulty devices to find their way to end users.
FIG. 1 shows a typical prior art input protection device used in integrated circuits. As shown in FIG. 1, an integrated circuit includes input pin 21 and input buffer circuitry 23. Regardless of the type of input buffer 23 used, the semiconductor device will fail if input buffer 23 is damaged, such as from the application of an ESD pulse. The current transferred during the application of an ESD pulse to input pin 21 is typically on the order of milliamperes, sufficient current to destroy typical prior art input buffers.
In an attempt to reduce the damage caused by ESD, the prior art circuit of FIG. 1 includes Schottky diode 22 having its cathode connected to input pin 21 via node 27, and its anode connected to ground. In this manner, when a negative-going ESD pulse is applied to input pin 21, Schottky diode 22 turns on, conducting current from ground to input pin 21. This clamps the input voltage to a predetermined negative voltage (typically -0.6 volts), thereby discharging the ESD pulse without allowing the voltage on node 27 to rise to a damaging level. However, while Schottky diode 22 is quite effective in discharging negative ESD pulses of great magnitude (often as high as about 6000 volts), it is less effective in protecting input buffer 23 from damage due to positive ESD pulses.
When a positive ESD pulse applied to input pin 21 exceeds the breakdown voltage of Schottky diode 22 (typically 20 volts), reverse breakdown occurs, and the ESD pulse is discharged from input pin 21 to ground. With a positive ESD pulse having a magnitude greater than about 200 volts, a relatively large amount of power is dissipated by Schottky diode 22, thereby destroying Schottky diode 22 by shorting its cathode to ground. When this happens, the integrated circuit is destroyed because input pin 21 is now effectively connected to ground. Thus, while Schottky diode 22 serves to prevent damage to input buffer 23 due to negative ESD pulses, it is itself damaged by certain positive ESD pulses.
It is therefore desirable to shunt positive-going ESD pulses to VCC. However, it is desirable not to shunt positive ESD pulses to VCC by clamping input terminal 21 by using a diode having its anode connected to input terminal 21 and its cathode connected to VCC. Such a clamping technique prevents the use of input voltages much greater than VCC, and it is oftentimes desirable to construct an input circuit 23 which is responsive to such high voltages in order to enter a test mode. In other words, many integrated circuit devices, unbeknownst to the end user, are constructed in such a manner as to allow the manufacturer to perform specific tests by placing input voltages greater than VCC on selected input pins. These voltages range from approximately 11 to 14 volts over the complete military range of temperature and voltage levels for VCC, and allow the manufacturer to perform additional tests on the device without requiring additional input pins for this purpose. Yet another reason why input pins 21 cannot simply be shunted to VCC by a Schottky diode is that oftentimes, in a large system, certian parts will be powered down when not in use by lowering their power supply voltage VCC to ground. In this event, signals appearing on a bus which is connected to an input pin of a powered-down device would be shunted to the powered-down device VCC, namely 0 volts. Thus, a powered-down device would drag down the entire bus to which its input pins are connected, clearly an unattractive limitation.
Another prior art technique for preventing ESD damage to an input buffer is shown in the schematic diagram of FIG. 2a. Input protection circuit 30 is connected to input pin 31 and serves to discharge ESD pulses applied to input pin 31, thereby preventing ESD damage to input buffer 33. Schottky diode 22 provides protection against negative going ESD pulses, as previously described with regard to FIG. 1. As shown in FIG. 2a, input pin 31 is connected via node 37 to VCC terminal 38. NPN transistor 34 is connected in series with diodes 35 and 36 between VCC terminal 38 and node 37. The collector and base of NPN transistor 34 are connected together in order to cause NPN transistor 34 to form a zener diode having a breakdown voltage of approximately 6 volts. When a positive ESD pulse is applied to input pin 31, diodes 35 and 36 become forward biased, and the emitter-base junction of transistor 34 experiences zener breakdown at a zener voltage of about 6 volts. In this event, current flows from input pin 31 to VCC terminal 38, thereby discharging the ESD pulse and limiting the voltage applied to input buffer 33 to a voltage equal to VCC (typically 14 volts) plus the forward bias voltage drops of diodes 35 and 36 (typically about 0.85 volts each) plus the emitter-base breakdown voltage (zener voltage) of transistor 34 (typically 6 volts), for a total of about 21.7 volts. Once emitter-base breakdown occurs, diodes 35 and 36 and transistor 34 provide a resistive path between input pin 31 and VCC terminal 38, thereby providing a discharge path for the ESD pulse. The relationship between the voltage on input pin 31 and the current through the path formed by diodes 35 and 36 and transistor 34 is shown in FIG. 6 as line 6a. Of importance, the resistance provided by this path is relatively large, and thus causes an attendant increase in the voltage received by input buffer 33 for large ESD pulses. Such prior art circuits have proven to be useful in preventing damage to Schottky diode 22 for ESD pulses as high as about 1,000 volts. However, above this level of ESD pulses, the relatively high resistance of the circuit of FIG. 2a still allows excessive voltage to be placed on node 37, allowing Schottky diode 22 to be damaged.
FIG. 2b shows a typical layout for the prior art circuit of FIG. 2a. Metal interconnect 38 serves as VCC terminal 38 of FIG. 2a, having contact 34c to the collector-base region 34a of transistor 34. Metal interconnect 40 connects emitter 34b of transistor 34 via emitter contact 34d to cathode 35a of diode 35. Another metalization interconnect 41 connects anode 35b of diode 35 to cathode 36a of diode 36. Yet another metal interconnect 37 connects anode 36b of diode 36 to input pin 31 and input buffer 33. Unfortunately, this prior art layout provides a significant amount of device and contact resistance.
Heretofore, we have been discussing the requirements for protecting input circuits of an integrated circuit from damage caused by ESD. It is widely recognized that input structures are far more susceptible to damage caused by ESD than are integrated circuit output structures. FIG. 3 is a schematic diagram of a typical TTL output buffer which receives a digital signal on input terminal 11 and provides a TTL level output signal on output terminal 19. Schottky diode 21 helps clamp negative-going ESD pulses appearing on output terminal 19. Such output structures can also withstand very high positive ESD voltages, oftentimes in excess of 4,000 volts. The reason for this is that, for a positive ESD pulse applied to output terminal 19, pulldown transistor 16 breaks down in a BVCEX mode.
As is well known, the collector-emitter junction of a bipolar transistor will "break down" when the transistor turns on in response to leakage current flowing across the reverse biased collector-base junction, when that leakage current is sufficient to cause the transistor to turn on. Naturally, the higher the collector voltage with respect to the base, the greater this leakage current, and the more likely the collector-emitter "breakdown". The type of termination placed on the base is very important in determining the voltage which can be applied to the collector without causing collector-emitter "breakdown". Various terminations are shown in FIGS. 3a through 3d. Naturally, the highest collector-emitter breakdown voltage achieved when the base of the transistor is shorted to ground (BVCES), since collector-base leakage current is shunted to ground. The lowest collector-emitter breakdown voltage occurs when the base is left floating or "open" (BVCEO), since all of the collector-base leakage current is available to form base-emitter current which tends to turn on the transistor. Somewhere between these two extremes lies the case when the transistor base is terminated in a resistor to ground (BVCER), or when the base is terminated through another mechanism (BVCEX), as is shown in FIG. 3d in which the base is terminated through a resistor connected in a series with a Schottky diode.
However, prior to this invention input structures exhibiting a BVCEX break down were unknown as were the advantages of utilizing BVCEX breakdown in an input stage.